In an aspect of conventional semiconductor packaging technologies, such as integrated fan-out wafer level packaging (InFO-WLP), redistribution layers (RDLs) may be formed over a die and electrically connected to active devices in a die. In addition, a molding compound may be formed around the die to provide surface area to support the fan-out interconnect structures. For example, RDLs including circuit routing layers are typically formed over both the die and the molding compound.
In such semiconductor package structures, heat causes both die and the molding compound to expand at their respective coefficients of thermal expansion (CTE) during operation. It is tensile stress concentration that develops due to the CTE mismatch between the die and the molding compound. However, such stress could potentially damage the circuit routing layer. For example, crack or break under thermal stress may occur in the circuit routing layer so that a circuit failure results. Accordingly, there is a need semiconductor package structures that increases the reliability and protects the circuit routing layer against tensile stress.